描述

A02B-0319-C243

FPGA獲取并緩存四個視頻源的數(shù)據(jù)流。這些FIFO緩沖器由DDR3存儲器控制器清空并保存在DDR3存儲器中。一旦一個完整的視頻數(shù)據(jù)包存儲完畢，視頻處理器會向DDR3存儲器控制器申請數(shù)據(jù)，存儲器控制器讀取數(shù)據(jù)并將其傳到視頻處理器。視頻處理器對視頻數(shù)據(jù)進(jìn)行格式化和壓縮，并通過DDR3存儲器控制器寫回存儲器。當(dāng)一個視頻數(shù)據(jù)包全部處理完畢，并準(zhǔn)備通過PCIExpress接口進(jìn)行傳輸，DDR3存儲器控制器從視頻處理器獲取數(shù)據(jù)并將其傳到PCIExpress接口。DDR3存儲器接口控制器概述從零開始設(shè)計(jì)一個DDR3存儲器控制器是非常困難的。需要考慮許多特性之間的權(quán)衡和互相影響。使用一個經(jīng)驗(yàn)證的IP核可以省去了大量的開發(fā)、測試和調(diào)試時(shí)間，否則就需要花費(fèi)許多時(shí)間來進(jìn)行in-house設(shè)計(jì)開發(fā)。一個經(jīng)驗(yàn)證的IP核還可以減少后續(xù)支持的負(fù)擔(dān)，因?yàn)檫@將由專門的開發(fā)人員來支持。最重要的是，使用一個經(jīng)驗(yàn)證的IP核可以使設(shè)計(jì)師將精力集中在其設(shè)計(jì)的獨(dú)特特性上，從而向最終客戶交付高價(jià)值的產(chǎn)品設(shè)計(jì)。例如，LatticeECP3DDR3存儲器控制器IP核已經(jīng)通過了一個第三方驗(yàn)證套件的驗(yàn)證。該IP核使用LatticeECP3I/O協(xié)議板來實(shí)現(xiàn)并通過全部測試。展示了一個存儲器控制器的框圖。圖最上面的配置接口用于設(shè)置設(shè)計(jì)的各個選項(xiàng)。DDR3I/O模塊使用I/O基元來實(shí)現(xiàn)。指令譯碼模塊根據(jù)每個bank和每一行，對用戶指令進(jìn)行譯碼，產(chǎn)生內(nèi)部存儲器指令序列。指令應(yīng)用模塊將每條指令序列轉(zhuǎn)換為滿足目標(biāo)存儲器件功能和時(shí)序要求的存儲器指令。數(shù)據(jù)通路模塊與DDR3I/O模塊連接，并且在讀操作時(shí)產(chǎn)生讀數(shù)據(jù)和讀取數(shù)據(jù)有效信號。讀數(shù)據(jù)偏移校正模塊對齊每一條8位數(shù)據(jù)線上的數(shù)據(jù)，調(diào)整任何可能的時(shí)鐘偏移。這使得用戶端的讀數(shù)據(jù)總線與系統(tǒng)時(shí)鐘準(zhǔn)確校準(zhǔn)。寫調(diào)整模塊為了正確的捕獲數(shù)據(jù)，調(diào)整了DQS對CK的關(guān)系。ODT塊通過為任意或所有DDR3SDRAM器件提供單獨(dú)的終端阻抗控制，提高了存儲器通道的信號完整性。

產(chǎn)品承諾：
保?證?全新原裝進(jìn)口,
保?證?安全準(zhǔn)時(shí)發(fā)貨，
保?證售后服務(wù)質(zhì)量，
優(yōu)勢價(jià)格，大量現(xiàn)貨。

主營DCS系統(tǒng)配件
機(jī)器人系統(tǒng)配件
大型伺服系統(tǒng)配件
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專業(yè)銷售進(jìn)口DCS? PLC系統(tǒng)備件模塊

PLC模塊，可編程控制器，CPU模塊，IO模塊，AI模塊，通訊模塊。AB/施耐德/ABB/GE/本特利/西屋/英維斯/霍尼韋爾/黑馬/FU克斯波羅

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